One conventional microprocessor memory interface includes an address bus, a data bus, and a control bus. The microprocessor uses the address bus to send an memory address to the memory. The number of address signal lines in the address bus depends upon the number of addressable memory locations in the memory. The data bus is used to transfer data from the microprocessor to the memory during a write transaction and to transfer data from the memory to the microprocessor during a read transaction. The data bus typically has 8*n data signal lines, where n is a natural number. The control bus typically includes control signal lines such as write_enable (WE) that are used by the microprocessor to control the type of transaction at the memory (read or write) and such as a clock signal (clk) that is used to synchronise the transaction.
The current flash memory interface 10 used in NOKIA mobile telephones is illustrated in FIG. 1. The interface 10 has a dedicated 9-bit upper address bus 2 and a 16-bit multiplexed data/address bus 4. It also has a control bus 6 comprising: a system clock signal line (external clock) 3, a chip select signal line (CSX) 5, a read signal line (OEX) 7, an address valid signal line (ADVX) 9 and a Ready signal line 11.
During an initial phase of a memory access the dedicated address bus 2 conveys the 9 most significant address bits while the multiplexed bus 4 simultaneously conveys the 16 least significant address bits. The address bits are conveyed at the rising edge of a single external clock cycle. The address valid signal line (ADVX) 9 is asserted by the microprocessor when the multiplexed bus 4 is carrying address information. This signal is typically used to latch the address information from the address bus 2 and the multiplexed bus 4 into a latching device at the memory.
In a later part of the memory access, the address bus 2 is unused, while the multiplexed bus 4 is used to convey a data word per clock cycle. Four data words D0, D1, D2 and D3 are conveyed in series.
The interface also has a flow control mechanism that allows the memory to pace the data transfer by temporarily suspending it. The control bus includes a Ready signal line 11 that is controlled by the memory. The state of the Ready signal indicates whether or not a data word is to be transferred. The Ready signal is asserted high while continuing data transfer is possible and asserted low when continuing data transfer is suspended.
In FIG. 1 a read memory access is illustrated. The transfer of the data word D3 from the memory to the microprocessor is delayed while the Ready signal line 11 is asserted low by the memory. The Ready signal is asserted HIGH as the fourth data word D3 is transferred from the memory.
The Ready signal line 11 enables paced burst mode access to the memory including crossing internal memory page boundaries. In burst mode access the data is read as a burst of words, if necessary from different memory segments used in the internal organization of the memory. The Ready signal can be used to suspend the data transfer while the next memory segment is fetched.
It would be desirable to improve the above-described interface.